The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to interconnect structures for a chip and methods of forming such interconnect structures.
A back-end-of-line (BEOL) interconnect structure may be used to electrically connect device structures fabricated on a substrate by front-end-of-line (FEOL) processing. The BEOL interconnect structure may be formed using a dual damascene process in which via openings and trenches etching in a dielectric layer are simultaneously filled with metal to create a metallization level. In a via-first, trench-last dual damascene processing process in which a via opening is formed in a dielectric layer and then a trench is formed above the via opening, the via openings are unfilled during the etching process forming the trenches. In a single damascene process, the via openings and trenches are formed in different dielectric layers and filled separately with metal. The lowest metallization level of the BEOL interconnect structure may be coupled with the device structures by contacts formed using middle-of-line (MOL) processing. These contacts may be composed of cobalt, which may be prone to etching damage when forming the via openings and/or trenches of the lowest metallization level of the BEOL interconnect structure.
Improved interconnect structures for a chip and methods of forming such interconnect structures are needed.